1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device utilizing a crystalline semiconductor film formed by crystallizing an amorphous semiconductor film, and, in particular, to a semiconductor device of a thin film transistor (hereinafter referred to as a TFT) or the like and a method for manufacturing the semiconductor device. A semiconductor device in accordance with the present invention includes not only a device such as a thin film transistor (TFT), a MOS transistor, or the like, but also a display device having a semiconductor circuit constituted by these insulating gate type transistors and an electrooptical device such as an image sensor, or the like. In addition, the semiconductor device in accordance with the present invention includes an electronic device mounted with the display device and the electrooptical device.
2. Description of the Related Art
Since a TFT can be formed on a transparent glass substrate, a development of applying the TFT to an active matrix type display device has actively been made. The active matrix type display device displays an image of high definition by controlling an electric field applied to liquid crystal in a matrix by a plurality of pixels arranged in the form of a matrix. Since the TFT utilizing a crystalline semiconductor film has a high mobility, it is possible to realize a high-resolution image display by integrating a functional circuit on the same substrate.
The active matrix type display device needs one million TFTs only for pixels so as to produce a high-resolution image display and needs the more TFTs to add a functional circuit in addition to the pixels, and in order to operate a liquid crystal display device stably, it has been necessary to ensure the reliability of each TFT and to operate it stably.
Since the specification required of an actual liquid crystal display device (also, referred to as a liquid crystal panel) is severe, in order to operate all pixels normally, pixels and drivers need to be of high reliability. In particular, when abnormal conditions occur in a driver circuit, a malfunction occurs in one column (or one row) of the pixel to cause a line defect.
Also, it is said that a TFT utilizing polysilicon is not comparable in reliability to a MOSFET (which is a transistor formed on a single crystal semiconductor substrate) used for an LSI or the like. There is a growing feeling that it is difficult to make an LSI circuit of the TFT unless this weakness is overcome.
The present applicant thought that a MOSFET had three advantages in reliability for the following reasons. FIG. 13(A) is a schematic view of a MOSFET. Reference numeral 1 designates a drain region formed on a single crystal silicon substrate, a numeral 2 designates a light doped drain region (hereinafter referred to as an LDD region), numeral 3 designates a field insulating film, and numeral 5 designates a gate insulating film 5 under a gate wiring 4.
Here, the present applicant thought that the MOSFET had three advantages. The first advantage is that there is a gradient in an impurity concentration from an LDD region 2 toward a drain region 1. As shown in FIG. 13(B), an impurity concentration increases from an LDD region 2 toward a drain region 2 in a conventional MOSFET. The present applicant thought that this gradient was effective in improving the reliability of the MOSFET.
Next, the second advantage is that the LDD region 2 overlaps a gate wiring 4. A gate overlapped light-doped drain (hereinafter referred to as GOLD) or a large-tilt-angle-implanted drain (hereinafter referred to as LTAID) is well known as such a structure. This structure can reduce the impurity concentration in the LDD region 2 and can increase an electric field relaxation effect, thereby increasing a hot carrier resistance.
Next, the third advantage is that there is a certain distance between the LDD region 2 and the gate wiring 4. This is because a field insulating film 3 sinks under the gate wiring 4. That is, since the thickness of the gate insulating film increases only at an overlapping portion, it is expected that the electric field will be effectively relaxed.
As described above, it is thought that the conventional MOSFET has some advantages compared with the TFT and hence has high reliability.
Also, an attempt has been made to apply these advantages of the MOSFET to the TFT. For example, M. Hatano, H. Akimoto, and T. Sakai realized a GOLD structure using a side wall formed of silicon, which was disclosed in IEDM97 TECHNICAL DIGEST, p523-526, 1997.
However, the structure disclosed in that paper presents a problem that an off-current (a current flowing when a TFT is in an off-state) increases compared with the conventional LDD structure and hence it was necessary to take countermeasures against the problem.
As described above, the present applicant thought that the problem in the structure of the TFT had an effect on the reliability thereof (in particular, a hot carrier resistance) when a comparison was made between the TFT and the MOSFET.
The present invention provides an art for overcoming the problem. It is an object of the present invention to realize a TFT having reliability equal to or higher than the reliability of the MOSFET. It is another object of the present invention to realize a highly reliable semiconductor device having a semiconductor circuit formed of such a TFT.
In order to solve the problems described above, a thin film transistor in accordance with the present invention has an n-type or a p-type first impurity region which functions as a source region or a drain region, and in addition to the first impurity region, two kinds of impurity regions (a second impurity region and a third impurity region) showing the same conductive type as that of the first impurity region, between the channel forming region and the first impurity region in a semiconductor layer in which a channel forming region is formed. The second impurity region and the third impurity region are lower in the concentration of the impurities which determines the conductive type than in the first impurity region and then function as high resistance regions.
The second impurity region is a low-concentration impurity region with a GOLD structure in which it overlaps a gate electrode via a gate insulating film and has an action of improving a hot carrier resistance, whereas the third impurity region is a low-concentration impurity region in which it does not overlap the gate electrode and has an action of preventing an increase in an off-current.
In this respect, in the present specification, a gate electrode is an electrode which crosses the semiconductor layer with an insulating film sandwiched therebetween and which applies an electric field to the semiconductor layer to form a depletion layer. In other words, a part of the gate wiring which crosses the semiconductor layer with an insulating film sandwiched therebetween is the gate electrode.
A constitution of the present invention disclosed in the present specification is a semiconductor device including a thin film transistor comprising a semiconductor layer, a gate insulating film formed on the semiconductor layer, and a gate electrode crossing the semiconductor layer via the gate insulating film, wherein the gate electrode is formed of a multilayer film including a first conductive layer, a second conductive layer, and a third conductive layer laminated in sequence on the gate insulating film, and wherein the semiconductor layer has a channel forming region and a pair of impurity regions of a conductive type and formed on both sides of the channel forming region, the pair of impurity regions partially overlapping the gate electrode via the gate insulating film.
Further, another constitution of the present invention is a semiconductor device including a thin film transistor comprising a semiconductor layer, a gate insulating film formed in contact with the semiconductor layer, and a gate electrode crossing the semiconductor layer via the gate insulating film, wherein the gate electrode is formed of a multilayer film including a first conductive layer, a second conductive layer, and a third conductive layer laminated in sequence on the gate insulating film, and wherein the semiconductor layer has a channel forming region, a first impurity region of a conductive type, a second impurity region which is sandwiched between the channel forming region and the first impurity region, is adjacent to the channel forming region and overlaps the gate electrode via the gate insulating film and has the same conductive type as the first impurity region and is lower in the concentration of impurity of the conductive type than the first impurity region, and a third impurity region which is sandwiched between the first impurity region and the second impurity region, does not overlap the gate electrode, has the same conductive type as the first impurity region, and is lower in the concentration of impurity of the conductive type than the first impurity region.
Further, still another constitution of the present invention is a semiconductor device including a CMOS circuit comprising an n-channel type thin film transistor and a p-channel type thin film transistor, wherein the CMOS circuit has a gate wiring crossing the semiconductor layer of the n-channel type thin film transistor and the semiconductor layer of the p-channel type thin film transistor via a gate insulating film, the gate wiring being formed of a multilayer film including a first conductive layer, a second conductive layer, and a third conductive layer laminated in sequence on the gate insulating film, the semiconductor layer of the n-channel type thin film transistor having a channel forming region, a first n-type impurity region, a second n-type impurity region which is sandwiched between the channel forming region and the first n-type impurity region, is adjacent to the channel forming region, overlaps the gate wiring via the gate insulating film, and is lower in the concentration of n-type impurity than the first n-type impurity region, and a third n-type impurity region which is sandwiched between the first n-type impurity region and the second n-type impurity region, does not overlap the gate wiring, and is lower in the concentration of the n-type impurity than the first n-type impurity region.
Also, a method of manufacturing a semiconductor device embodying the present invention comprises the steps of: forming a semiconductor layer; forming an insulating film on the semiconductor layer; forming a first photoresist mask which contacts the insulating film and crossing the semiconductor layer; a first addition of adding impurities of a predetermined conductive type to the semiconductor layer via the first photoresist mask; forming a gate electrode crossing the semiconductor layer via the insulating film, wherein the gate electrode is formed of a multilayer film including a first conductive layer, a second conductive layer, and a third conductive layer which are laminated in this order on the insulating film; forming a second photoresist mask which covers the gate electrode and is wider in the direction of the length of a channel than the gate electrode; and a second addition of adding impurities of the conductive type to the semiconductor layer via the second photoresist mask.